(1) Field of the Invention
The present invention relates to a semiconductor memory device and a method of reading data from the semiconductor memory device. In particular, the present invention relates to a semiconductor memory device which is arranged to read and output a plurality of data pieces at a time and the method of reading a plurality of data pieces from the semiconductor memory device and outputting them at a time.
(2) Description of the Related Art
For a memory such as a DRAM or a SRAM, a 2-bit prefetch operation has been proposed as a method of reading data from such a memory. The 2-bit prefetch is executed to read 2-bit data from memory cells at a time and continuously output the data to the outside (which is called a gapless read). However, when a reading operation is shifted from a word-line address being currently processed into the next word-line address, the reading operation needs to take a time in switching one word line to another. This switching time also needs a wait cycle in outputting the data. This thus makes it impossible to realize the gapless read. The partial improvement of the 2-bit prefetch for overcoming this shortcoming leads to a 4-bit prefetch.
FIG. 12 illustrates a schematic view of a memory cell array. FIG. 13 is a timing chart showing an operation of reading data from the memory cell array shown in FIG. 12 through the effect of the 4-bit prefetch.
A circle shown in FIG. 12 indicates a memory cell. WL0, . . . , WLj, WLk, . . . , WLm (j, l and m are a positive integer) indicate the word-line addresses of the memory cells, respectively. BL0, . . . , BLn (n is a positive integer) indicate the bit-line addresses, respectively.
The clock CLK shown in FIG. 13 indicates a synchronous clock. In synchronous to the clock, the memory device is operated. AVD# denotes an initial address read signal which indicates a start signal of reading an external address. An address ADD denotes a series of addresses generated on an external address read from the outside. In an Ax, y of the address ADD, an “x” portion denotes a word-line address of a memory cell and a “y” portion denotes a bit-line address thereof. A data DATA denotes data of a memory cell to be outputted. In a Dx, y of the data DATA, an “x” portion denotes a word-line address of the memory cell in which data is stored and a “y” portion denotes a bit-line address thereof. A word-line signal WL denotes a word line of a memory cell to be selected when data is read out and its timing. WLj and WLk shown in FIG. 13 correspond with the word-line addresses of the memory cells shown in FIG. 12, respectively. A sensing SNS denotes a bit-line address at which data being outputted from a memory cell is sensed and its sensing timing. BLn−3 to BL7 correspond with the bit-line addresses of the memory cells shown in FIG. 12, respectively. In FIG. 13, arrows denote synchronous timings between a clock CLK and a data DATA and between a clock CLK and a sensing SNS.
As shown in FIG. 13, the memory device obtains an external address on the timing of the initial address read signal AVD# and generates the continuous addresses Aj, n−3 to Aj, n as indicated in the address ADD. Then, based on the address Aj, n−3 to Aj, n, the memory outputs a word-line signal WL of the word-line address WLj onto the memory cell and then senses the bit-line address BLn−3 to BLn. As a result, as indicated in the data DATA, the data Dj, n−3 to Dj, n of the memory cells at the bit-line addresses BLn−3 to BLn on the word-line address BLj are outputted to the outside of the memory.
When the address ADD shifts to the address Ak, 0 to Ak, 3, the memory outputs a word-line signal WL of the word-line address WLk to a memory cell and then senses the bit-line addresses BL0 to BL3 as indicated in the sensing SNS. Thus, as indicated in the data DATA, the data Dk, 0 to Dk, 3 of the memory cells at the bit-line addresses BL0 to BL3 on the word-line address WLk are outputted to the outside.
For the 4-bit prefetch, as shown in FIG. 13, the word line may be switched from one to another while the 4-bit data is being outputted. This switching results in efficiently realizing the gapless read. However, in some cases, the 4-bit prefetch may not realize the gapless read. FIG. 14 illustrates the timing on which the gapless read may not be realized. As shown, in a case that the first access to a memory cell starts at a bit-line address BLn−1 located within four bits from the last bit-line address BLn of the word-line address WLj, while the 2-bit data Dj, n−1 to Dj, n are being outputted, it is necessary to switch the word-line address WLj to the other word-line address WLk. Hence, even the 4-bit prefetch needs a wait cycle.
Moreover, as a memory, a semiconductor memory device has been proposed which is arranged to provide two memory cell arrays whose word lines are shifted alternately so that data may be outputted without having to switch an address signal from the outside. The conventional prefetch has a disadvantage that no gapless read may be realized and the data output is made slower accordingly.
In the semiconductor memory disclosed in the Official Gazette of the Japanese Unexamined Patent Publication No. 04-157693, the semiconductor memory is equipped with two memory cell arrays and thus two systems of the relevant wirings and circuits like decoders. This double system results in disadvantageously making the circuit area larger.